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Timing advance offset

Created: May 16, 2021 08:51:06Latest reply: May 21, 2021 07:26:03 410 3 0 0 0
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HI all,

For upling timing, timing advance is needed for time delay due to distance between UE and gNB.

There is TA offset for UL/DL switching as I know.

However, I can not fully understand why does that offset is considered?

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BetterMing
Created May 16, 2021 09:05:49

Hello, dear.
In EN-DC, NR-DC, NE-DC and NR-SA operation modes, timing advance is initiated from GNB to UE, including MAC messages, and adjustments are made to the timing advance. For timing advance commands received in slot n, the UE shall adjust its uplink transmission timing advance command at slot n+k+1, which is configured as an add-on
In PDSCH DM-RS, the symbol duration (milliseconds) corresponding to the PDSCH processing time of UE processing capability 1 is the symbol duration (milliseconds) corresponding to the PUSCH preparation time of UE processing capability 1. Is the maximum timing advance value (millisecond) that can be provided by the 12-bit bitta command field, is the number of time slots in each sub-frame, and is the duration of sub-frame (1 millisecond). This has to do with configuring the smallest SCS of all ascending BWPs and descending BWPs.
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Hello, dear.
In EN-DC, NR-DC, NE-DC and NR-SA operation modes, timing advance is initiated from GNB to UE, including MAC messages, and adjustments are made to the timing advance. For timing advance commands received in slot n, the UE shall adjust its uplink transmission timing advance command at slot n+k+1, which is configured as an add-on
In PDSCH DM-RS, the symbol duration (milliseconds) corresponding to the PDSCH processing time of UE processing capability 1 is the symbol duration (milliseconds) corresponding to the PUSCH preparation time of UE processing capability 1. Is the maximum timing advance value (millisecond) that can be provided by the 12-bit bitta command field, is the number of time slots in each sub-frame, and is the duration of sub-frame (1 millisecond). This has to do with configuring the smallest SCS of all ascending BWPs and descending BWPs.
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  • convention:

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