Synchronous Ethernet<?xml:namespace prefix = "o" ns = "urn:schemas-microsoft-com:office:office" />

1 Introduction

Synchronous Ethernet is a technology used to recover the clock from the bit stream on an Ethernet link. As an asynchronous system, the Ethernet can function properly without a high-precision clock. Consequently, Ethernet devices were not provided with high-precision clocks, instead low-precision (100 ppm) clock signals were transmitted to save costs. Actually, the Ethernet uses serial code streams to transmit clock signals at the physical layer just as the SDH does, and the receiver must be able to recover the clock. The clock recovery function of the Ethernet was thus ignored, but it does not mean that the Ethernet cannot transmit high-precision clock.

Implementation of the synchronization Ethernet is quite simple. A device needs a clock module (or clock board) to provide a high-precision (4.6 ppm) system clock for all Ethernet interface cards. The PHY component of each Ethernet interface sends out data using this clock. PHY component of the receiver Ethernet interface recovers the clock, divides the frequency, and sends it to the clock board. The clock board checks the quality of the clocks reported by interfaces and selects the most precise one to synchronize the system clock with it.

2 Principles

On the synchronization Ethernet, clock signals are transmitted at the physical layer, as shown in Figure 2. The device requires a clock module, that is, a clock pinch board, to send high-accuracy system clock signals to all the Ethernet interface line cards.

·         In the receiving direction, the PHY chip of an Ethernet interface line card extracts and restores the clock signals sent from the line, divides the frequency, and sends the clock signals to the clock pinch board. The clock pinch board selects the clock with the highest accuracy as the reference clock source according to the SSM protocol and other related information, and then sends the clock source to phase-locked loop (PLL). The PLL traces this reference clock source and sends high-accuracy clock signals to each interface line card.

·         In the sending direction, the PLL on an Ethernet interface line card traces the clock source sent from the clock pinch board and generates the reference clock for data sending of the PHY chip.

Through the preceding process, clock frequency signals can be transmitted at the physical layer. The SSM quality level of the Ethernet clock is transmitted through dedicated SSM frames.

On the device, clock signals are transmitted as follows:

1.   Clock signals from different clock sources are sent to the clock pinch board. The clock pinch board of the device can obtain clock signals from the following components:

·      Line clock

The switching chip on the LPU of the device can obtain clock signals from an optical interface, and then sends the clock signals to the clock pinch board on the main control board through the circuit on the backplane.

·      External clocks, such as the building integrated timing system (BITS) clocks

·      The high-accuracy oscillator of the clock pinch board, which is used in emergencies when neither the LPUs nor the external clocks can provide the clock source

2.   The clock pinch board selects the best clock source from the received clock signals, and then sends 19.44 MHz clock signals to all LPUs through the downlink circuits on the backplane.

3.   The switching chip of each LPU uses this clock signal as the drive clock signal to send and receive packets.

3 Synchronization Status Message

To select the clock source correctly, devices on the network also transmits the Synchronization Status Message (SSM) with the clock information. On the SDH network, the quality level of the clock is transmitted through out-band overhead byte in the SDH frame. There is no out-band tunnel on the Ethernet. Therefore, the upstream device sends SSM messages to notify the downstream device of the quality level of a clock.

The SSM is used to transmit the quality level of timing signals on the synchronization timing link. A node on the Synchronous Digital Hierarchy (SDH) network or clock synchronization network can obtain the clock information of the upstream device by parsing the SSM message. The node performs operations such as tracing, switching, or holding the local clock source according to the SSM message, and then forwards the SSM message to the downstream device. The SSM message contains a 4-bit code, which can express 16 types of signals to indicate different quality levels.

4     Clock source selection

BITS

The BITS clock is an accurate external clock. The accuracy levels of clocks in descending order are: BITS clock, line (circuit) clock, and clock generated by the local oscillator of the clock pinch board. The clock pinch board provides two BITS interfaces, which can receive clock signals from two sources or obtain clock signals from the circuit.

Clock Input Modes

The following clock sources can provide input clock signals:

·     External clock

·     Line clock

·     Oscillator of the clock pinch board

The device supports three clock source selection modes, as described in Table1 

Table 1 Clock source selection modes

Mode

Description

Without the SSM quality level

·         This mode is used when the line clock or external clock does not provide the SSM quality level or when the quality level of each line clock source is already known. For example, if you know that the quality level of clock A is higher than the quality level of clock B, you can set a higher priority for clock A.

·         The system selects the clock source according to the priority that you set for each clock source. The clock source with the highest priority is selected.

With the SSM quality level

·         This mode is used when most of the line clock sources have SSM quality levels.

·         The system selects the clock source with the highest SSM quality level. When two clock sources have the same SSM quality level, the one with higher priority is selected.

Extended mode with the SSM quality

·         The system selects the clock source in the same way as the second mode.

·         The lower four bits of the S1 byte indicate the SSM quality level.

The higher four bits are used to transmit the clock source ID. The clock source ID prevents timing loops, where the output timing signal is sent back to the sender.

In the preceding modes, through running related commands, you can perform manual switchover or forcible switchover to select a specific clock.

The selected clock signal is then sent to all LPUs through circuits on the backplane so that all LPUs obtain an accurate clock signal. The clock signal is then sent to the downstream network through interfaces on the LPUs.

5 Working Modes of the Clock Chip

The clock chip can work in any of the following modes:

·     Tracing

If a BITS clock or line clock is selected as the clock source, the clock chip needs to trace and lock the clock frequency. This task is performed by the PLL.

·     Hold-in

When tracing an external clock (a BITS clock or line clock), the clock chip keeps saving the data of the clock. When the external clock cannot be used as the clock source, the clock chip maintains the frequency of the clock source for a certain period (24 hours at most) according to the clock data saved previously. In permanent holding mode, the clock chip uses the last saved data as the output clock frequency.

·     Free running

In free running mode, the clock chip uses the clock generated by the oscillator as the external clock.

The SSM quality level is transmitted on the Ethernet through SSM messages. Generally, an interface sends an SSM message every second. If the interface does not receive any SSM message from the peer interface within five seconds, the system considers that the SSM quality level of the circuit on the peer interface is Do not use (DNU). That is, the clock of this circuit will not be selected.

6 Timing Loop Avoidance

A timing loop occurs when a clock receives its own clock signal. That is, the output signal of a clock becomes the input signal of the clock. Measures to prevent timing loops should be taken in the network design stage. Timing loops can be prevented in the following ways:

·     When a line (circuit) clock is selected as the clock source, you can set the SSM quality level of the clock to DNU in return direction to prevent timing loops that may occur on the peer device.

·     Use the extended clock source selection mode with the SSM quality level.

This mode is developed by Huawei and has been used as a standard in China. Implementation of this mode is as follows:

§  In synchronous Ethernet, the SSM quality level occupies only the lower four bits of the S1 byte and the higher four bits are idle. The ID of the clock source is transmitted through the higher four bits of the S1 byte.

§  In a simple ring network, the reverse path of the ring network will transmit clock signals if the path of the ring network is down. The ID of the clock source can prevent timing loops by signing the primary clock source so that the clock source is protected.

On a complicated network, however, clock source IDs cannot completely eliminate timing loops because there are only 16 clock source ID’s. In addition, the timing loops generated on a subnet that does not contain the origin clock source cannot be prevented. To prevent timing loops more effectively, you can use the clock source IDs to separate the subnets.

§  A complicated network can be divided into two or more subnets. On a subnet, the clock source IDs are allocated by the network designer. As  a  common networking mode, in which two rings are connected through two links. There are two available reference clock sources on the entire network. If you set IDs only for the two reference clock sources, the IDs cannot be terminated on the right ring when the links between the two rings fail because the IDs come from the left ring. In this case, a timing loop occurs.

The solution is as follows:

Divide the network into two subnets, namely, left ring and right ring.

·     Specify the master and slave BITS clocks on the left ring and set IDs for the BITS clocks.

·     Specify the two links as the master and slave reference clock sources for the right ring.

By setting clock source IDs, you can separate the left and right rings logically. On network element C on the right ring, set an ID for link ‘a’. Similarly, set an ID for link ‘b’ on network element D. If faults occur on link ‘a’ and link ‘b’, no timing loop is generated because the right ring has clock source IDs.

The clock source IDs set on the right ring identify the reference clock sources and separate the right ring from the left ring. The clock source IDs set on the left ring cannot be sent to the right ring through link ‘a’ and link ‘b’, and the right ring can receive only the SSM quality level from the left ring.

The clock source IDs set on the right ring can be the same as the IDs set on the left ring, solving the problem of a limited number of IDs.

7    Advantages and Disadvantages of Sync-E

Advantages:

·           The quality of the recovered clock is 0.01 ppm, which is close to the quality of the SDH clock.

·           Sync-E is hardly affected by the PSN network and thus has high reliability.

·           The architecture of the clock system is similar to the architecture of the SDH solution and is mature.

Disadvantages:

·           Sync-E needs to be deployed on all the nodes on the network, which requires high expenses in network reconstruction.

·           Sync-E does not support time synchronization (phase synchronization).