The SDH system adopts bit interleaved parity (BIP) to detect bit errors. The BIP is performed on the BIP matrix of the regenerator section (RS), multiplex section (MS), higher order path, and lower order path using the B1, B2, B3, and V5 bytes respectively.
Bit errors are detected through the parity check of B1, B2, B3 and V5 bytes.
Error detection relationship and location.
RST is regenerator section termination.MST is multiplex section termination.HPT is higher order path termination.LPT is lower order path termination.
Bit errors that occur in the lower order path cannot be detected in the higher order path, MS, or RS. If bit errors occur in the RS, bit errors are triggered in the MS, higher order path, and lower order path
