Physical Layer Clock Synchronization is a process that clock frequency are recovered directly from physical signal. Digital signal transmitted on lines or links are coded or scrambled to reduce consecutive 0 or 1. Therefor, the code stream carries clock information. 
The clock source is a signal source carrying timing reference information. To achieve clock synchronization, an NE keeps its local clock in phase with the timing information by using the phase-lock loop. Clock source protection is implemented based on the priorities configured in the clock source priority list.
To achieve clock synchronization, an NE keeps its local clock in phase with the timing information by using phase-locked loop.
The configuration request a master and a slave NE. By default, the master NE traces the synchronous Ethernet clock and the slave NE traces the microwave link clock.
