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PLA
The mechanism of PLA switching triggered by link faults and that triggered by equipment faults are different.

If an ISV3 board is used, the shaping function of the packet switching unit is implemented on the ISV3 board.
In the following, two single-channel IF boards are used as an example to illustrate the switching principle.
Before PLA Switching
As shown in Figure 1, the packet switching unit performs shaping for Ethernet traffic based on the real-time Ethernet bandwidth provided by the PLA group, and transmits the Ethernet traffic to the IF board where the main port is located through the backplane bus.
The PLA module on board A runs the traffic balancing algorithm and schedules Ethernet traffic to boards A and B based on the real-time bandwidth provided by board A and that provided by board B.
The MUX unit combines the Ethernet traffic on the radio link where the main port is located (referred to as the main radio link), the Native TDM traffic, and overheads on the main radio link as microwave frames. The modem unit processes (such as modulates) the microwave frames and sends the frames to the ODU.
The PLA module on board A transmits the Ethernet traffic on the radio link where the slave port is located (referred to as the slave radio link) to the board B through the HSM bus. The MUX unit on board B combines the Ethernet traffic on the slave radio link, the Native TDM traffic, and overheads on the slave radio link as microwave frames. The modem unit processes (such as modulates) the microwave frames and sends the frames to the ODU.
board B transmits information such as its air-interface working mode and Ethernet service bandwidth to board A. board A dynamically adjusts traffic on the main and slave radio links based on the real-time bandwidth provided by the main and slave radio links each. In addition, board A calculates the total Ethernet bandwidth provided by the PLA group and transmits the result to the packet switching unit. In this manner, the PLA module on board A is capable of dynamically and evenly scheduling traffic between boards A and B.
In the receive direction:

The receive buffer in the PLA module enables Ethernet packets to be received and transmitted in the same time sequence.
The MUX unit on the main IF board A' extracts the Ethernet traffic and transmits the traffic to the PLA module.
The PLA module on board A' receives the Ethernet traffic that is separated by the MUX unit on the slave IF board B', through the HSM bus.
The PLA module on board A' align and decapsulates frames contained in the Ethernet traffic separated from boards A' and B', and transmits the traffic to the packet switching unit through the backplane bus.
Ethernet Bandwidth Adjustment
As shown in Figure 2, if the Ethernet bandwidth provided by the slave radio link decreases, board A transmits OAM packets to the packet switching unit, notifying the current traffic volume. Based on the received traffic volume, the packet switching unit performs shaping for the Ethernet traffic to ensure that appropriate Ethernet traffic volume is transmitted over board A. At the same time, the PLA module on board A allocates less Ethernet traffic to the slave radio link.
Figure 2 Ethernet bandwidth adjustment
After link protection switching
After a link in a PLA group fails, the PLA module responsible for allocating and scheduling traffic stops transmitting traffic to the failed link but transmits traffic only to the other functional link. In this case, only one link is available and therefore the PLA group provides lower Ethernet bandwidth.
As shown in Figure 3, if the main radio link fails, the PLA module on board A stops transmitting Ethernet traffic to the main radio link but transmits Ethernet traffic only to the slave radio link.
After the main radio link recovers, the PLA module on board A automatically enables Ethernet traffic to be transmitted on both the main and slave links.
Figure 3 After link protection switching principles(after switching)
After NE-level protection switching
Equipment faults (including cold resets) are classified into main IF board faults and slave IF board faults.
Main IF board faults:
As shown in Figure 4, if board A is faulty, the packet switching unit switches Ethernet traffic from board A to board B; the PLA module on board B is then responsible for scheduling the traffic.
As shown in Figure 5, after the fault on board A is rectified, Ethernet traffic will not be switched back from board B to board A. Instead, the PLA module on board B runs the traffic balancing algorithm and schedules traffic to boards A and B based on their real-time Ethernet bandwidth.
Slave IF board faults:
If board B is faulty, the LPA switching principles are the same as those used when the slave link fails.
Figure 4 NE-level protection switching principles (after switching)
Figure 5 NE-level protection switching principles (after the fault is rectified)
Configuration Process (PLA/EPLA/EPLA+/Super EPLA)
The core of configuring PLA/EPLA/EPLA+ is to configure a PLA/EPLA/EPLA+/Super EPLA protection group.

The OptiX RTN 905 s does not support this configuration.
The OptiX 910A, OptiX RTN 950A housing CSHO, and OptiX RTN 950 (housing CSHU/CSHUA) support EPLA+ only when working with ISV3/ISM6.
Only OptiX RTN 980 housing CSHN boards and OptiX RTN 950 housing CSH boards do not support EPLA.
When PLA/EPLA is implemented by stacking NEs, a PLA/EPLA group must be created on both the master and slave NEs.
For other PLA/EPLA configuration requirements, see Feature Dependencies and Limitations.
Detail
https://support.huawei.com/hedex/hdx.do?lib=EDOC110011342131180BCL&docid=EDOC1100113421&lang=en&v=02&tocLib=EDOC110011342131180BCL&tocV=02&id=EN-US_CONCEPT_0120617532&tocURL=resources%252Ffd%252Ftopic%252Ftc_rtn900_fd_1408.html&p=t&fe=1&ui=3&keyword=PLA
Thanks