Period for bit error detection in Poisson mode

17

According to the OTN standards, the period of the Poisson mode does not need to be set separately. It is related to the configured BER threshold. The difference is 10 times between two adjacent orders of magnitude. For example, 1E-3 corresponds to 10 ms, while 1E-4 corresponds to 100 ms.

Other related questions:
Bit error detection mechanism of a 2M tributary board
Bit error detection mechanism of a 2M tributary board: A 2M tributary board performs bit error detection for signals transmitting from a cross-connect board to the 2M tributary board, and does not perform bit error detection for 2 Mbit/s signals received from the PDH physical port on the 2M tributary board.

Service bit errors
Question: What may cause service bit errors? Analysis: None Root cause: None Answer: 1. Unreasonable dispersion compensation (not enough or too much); 2. Too high or too low incident optical power; 3. Performance deterioration of the transmit laser on the OTU board at the transmit end; 4. Severely contaminated pigtail connectors; 5. Changes in fiber attenuation; 6. Performance deterioration of the receive laser on the OTU board at the receive end. Suggestion and conclusion: None

Definition of SDH bit error performance
Definitions of SDH bit error performance: Background block error (BBE): an errored block not occurring as a part of an SES. Errored second (ES): Errored bit second: interval of 1 second during which a given digital signal is received with one or more errored bits according to G.821. Errored block second: interval of 1 second during which a given digital signal is received with one or more errored blocks according to G0.826. Errored second: errored bit second and errored block second. Severely errored second (SES): Severely errored bit second: interval of 1 second during which a given digital signal is received with an error bit ratio greater than 1 x 10-3 according to G.821 Severely errored block second: interval of 1 second during which 30% or more errored blocks exist or at least one defect exists according to G.826. Unavailable second (UAS): Unavailable second: An unavailable period starts from the first second of 10 consecutive SES events. These 10 seconds are considered as a part of the unavailable seconds. A new available period starts from the first second of 10 consecutive non-SES events. These 10 seconds are considered as a part of the available seconds. Consecutive severely errored second (CSES): Consecutive severely errored second: 2 to 9 consecutive SES events.

Whether higher-order bit errors can be detected when VC-4 does not carry services
Whether higher-order bit errors can be detected when VC-4 does not carry services: Higher-order bit errors cannot be detected when VC-4 does not carry services. They can be detected when VC-4 carries services.

Whether bit errors cause MSP switching
Whether bit errors cause MSP switching: The prerequisites for bit errors to trigger MSP switching are as follows: SD switching is enabled, bit errors are excessive, and there is no switching whose priority is higher than that of SD switching. MSP switching priority: Clear switching > Locked switching > Forced switching >SF switching (triggered by signal failures) > SD switching (triggered by bit errors) > Manual switching > Exercise switching. For details, see MSP switching conditions.

If you have more questions, you can seek help from following ways:
To iKnow To Live Chat
Scroll to top