Value of pre-FEC BER of the LWF board in FEC or AFEC mode on WDM 1600G devices that causes post-FEC BER

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When the pre-FEC BER reaches 10E�?, the bit error handling will be initiated. The error correction threshold of Huawei WDM devices can reach around 10E�? for FEC which meets the G.975 protocol standards, and reach around 10E�? to 10E�? for AFEC.

Other related questions:
Threshold of the pre-FEC BER that will trigger post-FEC bit errors on LWF boards using the FEC/AFEC function in BWS 1600G devices
When the pre-FEC BER reaches 10E-7, the system will start bit error processing. (The actual error correction limit of Huawei WDM devices can reach around 10E-5 for G.975-compliant FEC, and reach around 10E-3 to 10E-4 for AFEC.)

Permitted maximum pre-FEC BER of the FEC function
Theoretically, the maximum pre-FEC BER permitted by the FEC function for the OTU board is 8.27E-5.

FEC, AFEC, and super modules
FEC and AFEC are different encoding formats. The difference between the super board and non-super board lies in modulation formats. The AFEC and super modules are designed for adding the transmission distance of WDM equipment without regeneration. The following combinations are available: Common FEC Common FEC + Super module AFEC AFEC +Super module Signals of different modulation formats can be interconnected, while signals of different encoding formats cannot be interconnected. That is, OTU boards with and without the super module can be interconnected, but OTU boards of the AFEC and FEC encoding formats cannot be interconnected.

Interconnection and differences between FEC and AFEC on WDM equipment
AFEC is an enhanced forward error correction function, but FEC is a standard error correction function. The frame structures of the two functions are different and therefore cannot be interconnected.

Whether a board with FEC disabled can be interconnected with an OTU board that does not support FEC
Question: When the 73TRC board with FEC disabled is interconnected with the TWC board, the R_LOF alarm is reported at the receive end and services are unavailable, and even the R_LOS alarm is reported in some cases. Answer: 1. Functioning as a regeneration board of 73LWC, 73TRC also has the FEC function and has the same rate (2.66G) as 73LWC. After the FEC function is disabled on a board, FEC will not be performed at the receive end of the board; the signals transmitted at the transmit end, however, still contain FEC code. In other words, the board rate remains 2.66G. 2. You can use any of the following three methods to disable the FEC function of a board: Use the following command (applicable to NEs on the 5.0 platform): :cfg-set-fec: bid, port, path, enable/disable Use S3 DIP switches. S3.1 specifies the board type. 0: LWC 1: TRC S3.2 specifies whether FEC is configured. 0: with FEC 1: without FEC Use the :ptp,bid,f1,0; command. (The last byte 0 indicates that FEC is configured but 1 indicates that FEC is not configured.) For the 72LWC board, you can use only the PTP command because the board does not have S3 DIP switches. Use the :ptp:bid,b4,1; command. (The last byte 0 indicates that FEC is not configured but 1 indicates that FEC is configured.) Note: The meaning of the last byte in the command for the 71LWC board is opposite to that for the 72LWC board. The FEC setting and cancellation commands for the 71TRC board are the same as those for the 71LWC board, but the parameters are different. Command for setting the FEC mode: Ptp:slot ID,f1,2 (like S3.2 DIP switch setting to 0) Command for canceling the FEC mode: Ptp:slot ID,f1,3 (like S3.2 DIP switch setting to 1) 3. The regeneration boards as follows: The regeneration board of the TWC board is TWC, at a rate of 2.48G. The regeneration board of the 71LWC board is 71TRC, at a rate of 2.66G. The regeneration board of the 72LWC board is 72TRC, at a rate of 2.66G. The regeneration board of the 73LWC board is 73TRC, at a rate of 2.66G. Suggestion and conclusion: Assume that site A and site B are interconnected using an LWC board separately. LWC (A) ----- LWC (B) If you disable the FEC function of the LWC board at site A, the signals transmitted at the WDM side of the LWC board at site A remain unchanged, and the signal structure is still marked with FEC redundancy code and the rate is still 2.66G. However, the receive end on the WDM side of the LWC board at site A does not perform error correction. In this case, if the signals received by site A from site B contain bit errors, site A still transparently transmits the signals containing bit errors to the downstream site. Disabling the FEC function aims at testing the FEC coding gain of the board, rather than interconnecting with the boards that do not have the FEC function. The rate of 2.5G boards without the FEC function is 2.48G, whereas the rate of 2.5G boards with the FEC function is 2.66G. Therefore, the boards cannot be interconnected. Note that the FEC enabling status must be restored after the test.

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