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3D NAND Flash

Latest reply: May 28, 2022 14:29:03 486 26 12 4 0

3D NAND Flash

3D NAND is a type of non-volatile flash memory in which the memory cells are stacked vertically in multiple layers. The design and fabrication of 3D NAND memory is radically different than traditional 2D -- or planar -- NAND in which the memory cells are arranged in a simple two-dimensional matrix.

 

2D and 3D NAND basics

A flash memory cell is fundamentally a logic gate, and all logic gates use a well-understood binary input/output (I/O) relationship. The table that lists the relationship of logic gate inputs and output is called a truth table.

When Toshiba originally developed flash memory back in the 1980s, the memory devices were based on two distinctly different types of logic gates: NOR, which stands for not-OR, and NAND, which stands for not-AND. Both designs store data in memory cells built with floating gate transistors (FGTs).

Today, NAND has emerged as the most popular and widely used type of flash memory cell. The following two illustrations show basic NAND and NOR gates for students of basic digital electronics.

 

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Flash memory gained popularity due to its non-volatile nature. That is, each memory cell can retain its binary state, a logical zero or one -- the data -- without the need for continuous power. This is dramatically different than dynamic RAM (DRAM) where every memory cell must be continuously refreshed to retain its binary state. Non-volatile rewritable memory has provided convenient, portable memory devices for a wide range of devices such as imaging and video recording devices, thumb drives for transferring files and data, and practical solid-state drive (SSD) devices.

As with dynamic RAM, 2D flash devices are designed and fabricated with memory cells arranged in a horizontal two-dimensional matrix. This well-proven approach poses capacity and performance challenges because of limited space on the silicon die -- the chip itself. To increase storage capacity, the resulting memory cells must either be smaller, the die larger or both. Because memory cell fabrication can't get much smaller within the limits of today's fabrication technology, the resulting 2D flash device must get larger, presenting longer connections between memory cells that add latency and diminish performance. Thus, 2D flash devices are currently limited to capacities of 128 GB.

3D flash devices boost capacity and performance by stacking memory cells into vertical layers rather than a single horizontal layer. This effectively multiplies the available memory cells for a given area, enabling far greater storage capacities while using smaller footprint areas. In addition, the stacking enables shorter overall connections for each memory cell, which supports faster memory performance. 3D flash is a relatively new fabrication approach, but capacities of 256 GB and 512 GB are available with potential for far larger memory devices.

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How do flash and 3D NAND work?

Flash memory is an advanced type of electrically erasable programmable read-only memory (EEPROM) -- the kind of non-volatile memory that traditionally holds firmware such as the BIOS in a PC. Flash memory stores data in arrays of transistors, which can be designed to store one, two, three or four data bits. The metal-oxide semiconductor-based floating-gate transistors (FGTs) used to fabricate the memory cells employ two gates instead of one. One gate is a floating gate, and another gate is a control gate. In effect, the series of gates acts as a switch where the control gate captures electrons and moves electrons to the control gate. This kind of architecture enables the transistor to preserve the state of each memory cell when electrical power is removed.

As with older and more traditional EEPROMs, a flash memory cell must be erased before it can be rewritten. An EEPROM erases data byte by byte. In a flash memory device, tunneling electrons clear any charge on the floating gate in a flash -- thus, the name flash memory -- enabling contents to be rewritten.

NOR flash is architected to provide high-speed access to individual memory locations, making NOR well suited for tasks that depend on optimum speed and access such as modern PC firmware, effectively obsoleting older EEPROM-type devices. By comparison, NAND flash is designed to work with blocks of data called pages. This makes NAND flash well suited for high-speed sequential reads and writes for high-volume data activities such as video and images. NAND provides very fast read operation and is less expensive than NOR. Consequently, NAND flash is the predominant flash memory technology for many consumer and industrial devices.

Unlike DRAM, all-flash memory offers a finite number of erase/program cycles -- a characteristic referred to as endurance. The behavior of tunneling electrons used to erase the memory cell will eventually cause the memory cell to wear out and fail. As the cell wears out and cells fail, the overall design of the memory chip will work to relocate bad cells and bad blocks, resulting in more time needed to write -- program -- which slows the flash memory performance. Fortunately, the endurance of a modern flash memory device is many thousands of erase/program cycles. And this life is extended by wear-leveling techniques, which ensure that all of the memory is written before cells are erased, basically preventing the same subsets of memory cells from being erased and rewritten frequently while other areas of the chip are left relatively unused.

To make the move from 2D flash to 3D flash, the fabrication process adds multiple layers of memory cells on top of each other, along with interconnections between the layers. A typical 3D NAND flash chip can easily involve 32 to 48 individual layers, with 64-, 96- and even 128-layer devices coming. The addition of layers makes 3D flash more difficult and time-consuming to fabricate than 2D flash. However, layers enable far greater bit densities within the memory device with far shorter connection paths, which brings better performance.

Today, 3D NAND flash devices are commonplace in computers, such as tablets, as well as storage devices, such as USB (Universal Serial Bus) thumb drives, flash arrays and enterprise-grade SSDs.


Pros and cons of 3D NAND vs. 2D NAND

Both 3D and 2D NAND flash memory devices are readily available and in use today. But there are tradeoffs to consider when selecting the best technology for a storage task.

Capacity. 3D NAND flash offers greater storage capacity -- or data density -- compared to 2D NAND flash. Stacking multiple layers of memory cells to create a three-dimensional storage matrix can bring significantly greater storage capacity to the same chip area -- footprint. Similarly, denser chips can be built into denser, higher-capacity devices such as SSDs. For example, SSDs are readily available in 1 TB and 2 TB capacities.

Cost. Flash memory follows the same cost-per-byte relationship as other storage technologies, and 3D NAND flash can vastly lower the cost-per-byte when compared to 2D NAND flash. In 2017, a 2D NAND wafer created in a fabrication facility might have stored 1.6 TB, while a 3D NAND wafer might have stored more than 17 TB. Even if the 3D NAND wafer is nearly double the cost of a 2D NAND wafer, the dramatic capacity improvement of the 3D wafer makes the cost-per-byte far lower for the 3D NAND technology. This makes 3D NAND more cost-effective for many types of storage applications.

Performance and power. When memory cells are laid out in a 2D matrix, there is a finite distance to move bits to and from cells. This distance equates to time -- or latency. To increase the storage capacity of the 2D matrix, those distances -- and so the latency -- must also increase, effectively lowering the performance of larger 2D NAND flash devices. By stacking and interconnecting layers of NAND memory cells, the physical distance -- and, thus, the latency -- can be curtailed to maintain higher performance at higher storage capacities. In addition, 3D NAND flash memory can be written in a single pass and uses up to 50% less power than 2D NAND.

Manufacturing challenges. 3D NAND flash devices can be extremely difficult to fabricate, requiring thousands of individual processes to take a raw wafer through to completed dies, or chips. Errors or contamination at any part of the fabrication process can introduce bad cells and render entire dies unusable. Good manufacturing demands extraordinary precaution against contamination, extremely high manufacturing control and material purity.

Complex flash control. Although flash memory technology doesn't require refresh circuitry as with DRAM, flash does require sophisticated data management and error correction control to oversee the way that data is stored on a flash chip. For example, a 3D NAND flash might need to remap -- move -- an entire block -- page -- of storage if so much as a single bit fails, so circuitry is needed to check for bit failures. At the same time, additional control is needed for wear leveling spreading out the data stored throughout the chip to minimize erase/program cycles and extending the flash device's working life. These controls are more complex for 3D NAND versus 2D NAND.

NAND types

NAND technology can be broken down into several specific designs including

·        Single-level cell

·        Multi-level cell

·        Triple-level cell

·        Quad-level cell

Single-level cell. SLC stores one bit per memory cell. Because only one cell is involved in each erase/program cycle, the cells are erased and rewritten least-frequently on average, leading to some of the best endurance for NAND memory. A typical SLC device can be erased and rewritten about 60,000 times. In addition, the failure of a memory cell only affects that corresponding bit, making failures easier to remap/contain within the flash chip. Unfortunately, SLC is also the most expensive type of NAND flash and is often reserved for the highest-performance mission-critical enterprise tasks such as database applications.

Multi-level cell. MLC stores two bits per memory cell. This improves the capacity of the flash memory device and lowers the cost, because there are twice the number of bits per cell compared to SLC. But endurance is affected because two bits must be erased and rewritten when the cell is rewritten, so the cell wears out faster. An MLC device can be erased and rewritten between 1,500 to 3,000 times. Still performance and endurance are attractive for most general-purpose applications with modest I/O needs, and MLC is frequently used in everyday computing devices such as laptops. 3D NAND can employ MLC flash. Enterprise MLC is a variation on MLC, which provides enhanced wear leveling control, which improves overall endurance and makes the device better suited to enterprise environments.

Triple-level cell. TLC stores three bits per memory cell. This continued the push toward added flash capacity and lower costs, but the additional bit lowers performance slightly, and the erase/program cycle now affects three bits instead of one or two, lowering the device endurance even further. TLC is more frequently employed for read-heavy tasks where erase/program cycles are less frequent, helping to maximize endurance and preserve the working life of the TLC device. 3D NAND can employ TLC flash, and a typical 3D TLC device can be rewritten anywhere from 500 to 3,000 times.

Quad-level cell. QLC stores four bits per memory cell. This technology represents the highest capacity and lowest cost, but it also poses the lowest memory cell endurance and performance of any flash technology. Advanced error correction and wear leveling controllers help to extend QLC device endurance, and the technology can prove attractive for read-heavy tasks where rewrites are infrequent -- think archival storage. A typical QLC cell can be rewritten about 100 times, though wear leveling can improve this to about 1,000 times. 3D NAND can employ QLC flash.

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